Electronic devices are frequently driven by a clock signal. The clock signal provides a timing signal that causes electronic components to perform specific actions. For example, clock signals are frequently used by logic circuits to control the timing of reads and writes to memory devices, such as dynamic random access memory (DRAM), static random access memory (SRAM), electrically-erasable programmable read-only memory (EEPROM), read-only memory (ROM), and the like.
Ideally, the clock signal has sharp transition edges, i.e., the clock signal transitions from a low state to a high state quickly and transitions from a high state to a low state quickly. FIG. 1 illustrates one example of a preferred clock signal 100 that transitions from low-to-high within about 0.5-1.0 ns and transitions from high-to-low within about 0.5-1.0 ns. Shorter or longer times may be used for other applications. It is expected that the transition time will decrease as the size of the electronic devices decrease and processing speeds increase.
During testing, these electronic devices are often placed in a burn-in chamber or other test environments in which an external clock signal is provided to the electronic devices. The external clock signals are generally heavily loaded, causing the clock transitions to occur more slowly. It is not uncommon for an external clock signal to require 100 ns or more to transition from low-to-high and from high-to-low. This can be particularly troublesome when the system clock is designed to operate at faster rates, such as a 7.5 ns or a 2.5 ns clock for 133 MHz and 400 MHz designs, respectively.
Furthermore, to reduce the pin count required on the electronic device, clock signals are often compared to a reference voltage, such as Vdd/2 rather than a complementary voltage in testing modes. The reliance on a reference voltage makes the external clock, and thus the electronic device operations, more susceptible to noise. Noise is commonly caused by other electronic devices that are being tested in parallel.
For example, DRAM devices are frequently tested in groups wherein an external clock drives a plurality of DRAM devices. The heavy load on the external clock reduces the speed at which the external clock transitions from high-to-low and from low-to-high. Furthermore, the noise generated by the other DRAM devices being tested may cause noise on the external clock. The noise on the external clock frequently causes the clock to transition early. This is referred to as a slope reversal.
FIG. 2 illustrates one example of a problem that has been seen on an external clock signal 200. Preferably, the external clock signal 200 is compared to a reference voltage, indicated by dashed line 208. If the external clock signal 200 is above the reference voltage 208, then an internal clock signal is set high. If, on the other hand, the external clock signal 200 is below the reference voltage 208, then the internal clock signal is set low. Transitions from low-to-high and from high-to-low in about 100 ns are illustrated by the first three transitions. Noise on the external clock signal 200, however, may cause the external signal to transition prematurely, as illustrated by the slope reversals in region 210. When these slope reversals occur near the reference voltage 208, the clock may cycle from low-to-high or high-to-low in a time period significantly less than 100 ns. Shorter or longer transition times may be seen, and other slope reversals may occur at different times in the signal. These shorter cycle times may cause the device under test to fail.
Thus, there is a need for a device and a method of filtering a clock signal provided to an electronic device.